Vector instructions, once a powerful performance innovation of supercomputing in the 1970s and 1980s became an obsolete technology in the 1990s. But like the mythical phoenix bird, vector instructions have arisen from the ashes. Here is the history of a technology that went from new to old then back to new.
But first, a few definitions. A vector instruction is an SIMD instruction, Single Instruction Multiple Data. A vector instruction refers to vector registers where multiple data resides. For example, a Cray-1’s vector register contained up to 64 64-bit double-precision floating point numbers. The Cray-1 had eight of these registers. Many operations, for example: add and multiply can be issued to add or multiply two vector registers and place the result in a third vector register.
In 1976 Cray Research and Seymour Cray created the Cray-1, the first commercially successful supercomputer with vector instructions. The first Cray-1 was delivered to Los Alamos National Laboratory. There had been other vector computers before: The University of Illinois’s ILLIAC IV, Texas Instruments Advanced Scientific Computer (ASC), and Control Data Corporation’s STAR-100. But none of these was a commercial success. With the Cray-1, vector technology became mainstream in the supercomputer world. Compilers were developed to automatically vectorize loops.
The Cray-1 did not have a cache. The vector registers were the computational “way stations” between memory and the functional units. The functional units computed the mathematical operations – for example, add and multiply.
The vector instructions made good sense. They improved performance, were simple, reduced instruction encoding, reduced the calculation of addresses, and reduced instruction cache misses. Here’s a simple example, adding two arrays together:
C(i) = A(i) + B(i)
With a scalar CPU (Central Processing Unit), the loop looks like the following:
Here’s what the loop looks like with vector instructions:
Note that the vector loop saves 3*63 instruction calculations, 2*63 load instructions, 63 store instructions, 63 compare instructions, and 63 jump instructions for every 64 iterations of the CPU loop.
Cray Research continued with the Cray-1S (1979), Cray-1M (1982) and the Cray-XMP (1982) and was highly successful in the 1980s. In the mid-1980s, Fujitsu, Hitachi, and Nippon Electric Corporation (NEC) also introduced vector supercomputers.
A researcher at the Lawrence Livermore National Laboratory, Eugene D. Brooks, foretold the demise of the vector machines in 1990. His argument was simple: The Cray supercomputers were based on custom processors and he graphed the supercomputer’s peak FLOPS thru time.
FLOPS is an acronym for Floating Point Operations per Second. TFLOPS is 2 to the 40th power or approximately 10 to the 12th power FLOPS. GFLOPS is 2 to the 30th power or approximately 10 to the 9th power FLOPS. MFLOPS is 2 to the 20th power or approximately 10 to the 6th power FLOPS. And KFLOPS is 2 to the 10th power or approximately 10 to the 3rd power FLOPS. Then he graphed the progress of the microprocessor’s peak Giga-FLOPS thru time. The lines crossed at ~1990 with the microprocessors pulling ahead of the supercomputer processors. He presented this at Supercomputer 1990 and entitled his talk, “Attack of the Killer Micros.”
Dr. Brooks defined: “A killer micro is a microprocessor-based machine that infringes on mini, mainframe, or supercomputer performance” and noted that “Nobody will survive the attack of the killer micros.” The microprocessors used scalar instructions, not vector instructions; so the rise of the microprocessors was the demise of the vector processors.
There were several other factors that were significant. The fall of the Berlin wall in 1989 decreased US government spending for supercomputers. Also, Intel Corporation and Advanced Micro Devices (AMD) were selling microprocessor in high volumes, allowing them to sustain large research and development efforts to improve their microprocessors, a situation the supercomputer companies could not match. Intel has been able to sustain Moore’s Law (it’s actually an observation) for 50 years. Moore’s Law, named after Intel founder Gordon Moore, states that the number of transistors in a processor will double every two years (1965).
The re-emergence of vector instructions started with the MMX instruction set (1997) which was added to the x86 architecture and the Intel Pentium processors. The instructions were SIMD, but the vectors were small (64-bits), few (8 registers) and the operations were integer, no floating point. A single instruction could then be applied to two 32-bit integers, four 16-bit integers, or eight 8-bit integers at once.
The next SIMD addition was the Streaming SIMD Extension (SSE) to the x86 architecture and the Pentium III (1999). The SSE instruction set added eight new 128-bit registers and floating point operations were added. In all, SSE added 70 new instructions. A single instruction could then be applied to two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, 8 16-bit short integers, or sixteen 8-bit bytes.
These instructions sets were soon enhanced: SSE2 (2001), SSE3 (2004), SSSE3 (2006), SSE4 (2006), and SSE5 (2007).
The next SIMD addition was the Advanced Vector Extensions (AVX) in 2008. The SSE registers were increased from 128 to 256 bits and renamed for AVX. The number of registers was increased from 8 to 16. Do we spot a trend here? AVX introduced a three-operand instruction format which allowed preservation of the input registers. For example, a two-operand operation is a=a+b, which destroys the “a” input register. A three-operand operation is c=a+b, which preserves the “a” register. Again enhancements followed, AVX2 (2013) which added integer 256-bit SIMD instructions and a floating point fused multiply-add.
Currently, the newest supercomputer processor standard for vector instructions is AVX-512. The register length was expanded from 256 to 512 bits. The number of registers was expanded from 16 to 32. AVX-512 is supported in the Xeon Phi (Knights Landing) processor. These longer vectors support a peak of three TFLOPS in Knights Landing. Vectors were back!
One interesting way to look at the history of vector technology is to compare it to the dinosaurs, who arose in the Triassic Period, flourished in the Jurassic and Cretaceous Periods, and died out at the beginning of the Paleogene Period. This is a span of approximately 142 million years. Fortunately, the dinosaurs have not returned.
The vector processors arose in the 1970s and flourished until about 1990. The “Attack of the Killer Micros” correctly predicted their reign would end in the 1990s. But the vector processors started a comeback in 2000 with MMX and are flourishing in mainstream processors today. This is a span of approximately 50 years.
And the trends allow us a prediction of future mainstream processors; they will probably have more vector registers, more vector instructions, and the length of the vector registers will likely increase. You cannot keep a good idea down.
We’d love to chat about how vector instructions can be put to good use in your HPC environment. Just reach out for a conversation.
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